Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, ...
EDN

Jitter attenuation 101: How do you pick the right PLL bandwidth?

Clock signals provide reference timing to every integrated circuit and electrical system. While consumer applications typically use simple quartz crystals for reference-clock generation, other ...
Design-Reuse

Is there a "one-size fits all" SOC PLL?

A PLL (phase-locked loop) is perhaps the most widely used analog circuit in SOCs (system-on-a-chip). Almost all SOCs with a clock rate over 30MHz use a PLL for frequency synthesis. Most SOCs use more ...
Electronic Design

Select The Right PLL-based Oscillator For Your Timing Application

More than 10 years ago, the frequency control industry introduced PLL-based (phase-locked loop) oscillators, an innovation that pioneered several features previously unavailable with traditional ...
Design-Reuse

True Circuits Introduces Spread Spectrum and Low Bandwidth Phase-Locked Loop Hard Macros

LOS ALTOS, California, May 5, 2003 – True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor and systems industries, today announced ...