电子工程专辑

SystemVerilog|UVM|RAL寄存器模型操作图鉴

寄存器模型操作，指的是通过寄存器模型对RTL中寄存器进行读写访问，或者同步寄存器模型与RTL中寄存器的值。对寄存器模型的操作，可以通过调用模型提供的方法来实现。这些方法的调用，建立在已经完成寄存器模型的构建和集成到验证环境的基础上。
电子工程专辑

SystemVerilog|UVM|获取命令行参数的方法，这些就够用了

这是一篇技术干货快文，能够快速阅读完。文章内容是关于如何从命令行获取和解析参数，包括SystemVerilog本身支持的系统函数和UVM提供的函数封装，并给出示例代码和仿真结果。 通过命令行来传递参数在实际项目中算是常规操作，比如通过命令行参数来指定 ...
Design-Reuse

Improving SystemVerilog UVM Transaction Recording and Modeling

This paper will summarize previous work about SystemVerilog [1] UVM [2] transaction recording, transaction modeling and the supporting transaction recording APIs. This discussion will span a wide ...
Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...
EDN

New simulation capabilities advance SystemVerilog

Santa Cruz, Calif. — Two verification providers — Mentor Graphics Corp. and Axiom Design Automation — are claiming new simulation technology this week that offers broad support for the emerging ...
Design-Reuse

Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence

SystemVerilog [1] UVM [2] sequences [4][5] are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive ...
EDN

A short course on SystemVerilog classes for UVM verification

Learning any language can be difficult when so many words take on different meanings in different contexts. “Why does a farmer produce produce?” These homonyms can be confusing even for native ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...